ov965x_configure
Default mainpageat91libcomponentsomnivisionov9655ov965x_configure
Description Source Call Graph
Start Line: 77
void ov965x_configure(Twid *pTwid, unsigned int width, unsigned int heigth)
{
    const struct ov965x_reg *reg_conf;
    unsigned char goodCaptureSize = 0;
    unsigned char i;

    TRACE_DEBUG("ov965x_configure\n\r");
    for( i=0; i<sizeof(ov965x_sizes); i++ ) {
        if( ov965x_sizes[i].width == width ) {
            if( ov965x_sizes[i].height != heigth ) {
                TRACE_ERROR("ov965x_configure vsize not define\n\r");
            }
            else {
                goodCaptureSize = 1;
                break;
            }
        }
    }

    if( goodCaptureSize == 0 ) {
        TRACE_ERROR("Problem size\n\r");
        while(1);
        return;
    }

    // Default value
    reg_conf = ov9655_yuv_vga;

    // common register initialization
    switch(width) {
        case 1280: //SXGA
            TRACE_DEBUG("SXGA\n\r");
            reg_conf = ov9655_yuv_sxga;
        break;
        case 640: //VGA
            TRACE_DEBUG("VGA\n\r");
            reg_conf = ov9655_yuv_vga;
        break;
        case 352: //CIF
            TRACE_DEBUG("CIF\n\r");
            reg_conf = ov9655_yuv_cif;
        break;
        case 320: //QVGA
            TRACE_DEBUG("QVGA\n\r");
            reg_conf = ov9655_yuv_qvga;
        break;

        case 176: //QCIF
            TRACE_DEBUG("QCIF\n\r");
            reg_conf = ov9655_yuv_qcif;
        break;
        case 160: //QQVGA
            TRACE_DEBUG("QQVGA\n\r");
            reg_conf = ov9655_yuv_qqvga;
        break;
        case 88: //QQCIF
            TRACE_DEBUG("QQCIF\n\r");
            reg_conf = ov9655_yuv_qqcif;
        break;
        default:  
            TRACE_DEBUG("ov965x_configure problem\n\r");
        break;
    }
    ov965x_write_regs(pTwid, reg_conf);
}