Description
Source
Call Graph
Start Line: 55
void NorFlash_CFI_DumpConfigruation(struct NorFlashCFI *pNorFlashCFI)
{
unsigned char i;
TRACE_DEBUG("Common Flash Interface Definition Table\n\r");
TRACE_DEBUG("Addr. Data Description \n\r");
TRACE_DEBUG("0x10 %04Xh Query Unique ASCII string\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.queryUniqueString[0]);
TRACE_DEBUG("0x11 %04Xh \n\r",
pNorFlashCFI->norFlashCfiQueryInfo.queryUniqueString[1]);
TRACE_DEBUG("0x12 %04Xh \n\r",
pNorFlashCFI->norFlashCfiQueryInfo.queryUniqueString[2]);
TRACE_DEBUG("0x13 %04Xh Primary OEM Command Set\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.primaryCode);
TRACE_DEBUG("0x15 %04Xh Address for Primary Extended Table\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.primaryAddr);
TRACE_DEBUG("0x17 %04Xh Alternate OEM Command Set\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.alternateCode);
TRACE_DEBUG("0x19 %04Xh Address for Alternate OEM Extended Table\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.alternateAddr);
TRACE_DEBUG("0x1B %04Xh VCC min write/erase\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.minVcc);
TRACE_DEBUG("0x1C %04Xh VCC max write/erase\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.maxVcc);
TRACE_DEBUG("0x1D %04Xh VPP min voltage\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.minVpp);
TRACE_DEBUG("0x1E %04Xh VPP max voltage\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.maxVpp);
TRACE_DEBUG("0x1F %04Xh Typical timeout per single word write\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.minTimeOutWrite);
TRACE_DEBUG("0x20 %04Xh Typical timeout for Min. size buffer write\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.minTimeOutBuffer);
TRACE_DEBUG("0x21 %04Xh Typical timeout per individual block erase\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.minTimeOutBlockErase);
TRACE_DEBUG("0x22 %04Xh Typical timeout for full chip erase\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.minTimeOutChipErase);
TRACE_DEBUG("0x23 %04Xh Max. timeout for word write\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.maxTimeOutWrite);
TRACE_DEBUG("0x24 %04Xh Max. timeout for buffer write\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.maxTimeOutBuffer);
TRACE_DEBUG("0x25 %04Xh Max. timeout per individual block erase\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.maxTimeOutBlockErase);
TRACE_DEBUG("0x26 %04Xh Max. timeout for full chip erase\n\r",
pNorFlashCFI->norFlashCfiQueryInfo.maxTimeOutChipErase);
TRACE_DEBUG("0x27 %04Xh Device Size = 2N byte\n\r",
pNorFlashCFI->norFlashCfiDeviceGeometry.deviceSize);
TRACE_DEBUG("0x28 %04Xh Flash Device Interface description\n\r",
pNorFlashCFI->norFlashCfiDeviceGeometry.deviceInterface);
TRACE_DEBUG("0x2A %04Xh Max. number of byte in multi-byte write\n\r",
pNorFlashCFI->norFlashCfiDeviceGeometry.numMultiWrite);
TRACE_DEBUG("0x2C %04Xh Number of Erase Block Regions within device\n\r",
pNorFlashCFI->norFlashCfiDeviceGeometry.numEraseRegion);
for(i = 0; i < pNorFlashCFI->norFlashCfiDeviceGeometry.numEraseRegion; i++) {
TRACE_DEBUG("0x%2X %04Xh Number of Erase Blocks of identical size within region %x \n\r",
0x2D + i * 4, pNorFlashCFI->norFlashCfiDeviceGeometry.eraseRegionInfo[i].Y, i );
TRACE_DEBUG("0x%2X %04Xh (z) times 256 bytes within region %x \n\r",
0x2E + i * 4, pNorFlashCFI->norFlashCfiDeviceGeometry.eraseRegionInfo[i].Z, i );
}
}